Microchip Technology /ATSAML11D14A /CoreDebug /DEMCR

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Interpret as DEMCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (VC_CORERESET)VC_CORERESET 0 (VC_MMERR)VC_MMERR 0 (VC_NOCPERR)VC_NOCPERR 0 (VC_CHKERR)VC_CHKERR 0 (VC_STATERR)VC_STATERR 0 (VC_BUSERR)VC_BUSERR 0 (VC_INTERR)VC_INTERR 0 (VC_HARDERR)VC_HARDERR 0 (VC_SFERR)VC_SFERR 0 (MON_EN)MON_EN 0 (MON_PEND)MON_PEND 0 (MON_STEP)MON_STEP 0 (MON_REQ)MON_REQ 0 (SDME)SDME 0 (TRCENA)TRCENA

Description

Debug Exception and Monitor Control Register

Fields

VC_CORERESET

Core reset Halting debug vector catch enable

VC_MMERR

MemManage exception Halting debug vector catch enable

VC_NOCPERR

UsageFault exception coprocessor access Halting debug vector catch enable

VC_CHKERR

UsageFault exception checking error Halting debug vector catch enable

VC_STATERR

UsageFault exception state information error Halting debug vector catch enable

VC_BUSERR

BusFault exception Halting debug vector catch enable

VC_INTERR

Excception entry and return faults Halting debug vector catch enable

VC_HARDERR

HardFault exception Halting debug vector catch enable

VC_SFERR

SecureFault exception Halting debug vector catch enable

MON_EN

DebugMonitor enable

MON_PEND

DebugMonitor pending state

MON_STEP

Enable DebugMonitor stepping

MON_REQ

DebugMonitor semaphore bit

SDME

Secure DebugMonitor enable

TRCENA

Global DWT and ITM features enable

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